Many memory devices are compatible with the Inter-integrated circuit (I2C) protocol. The I2C protocol provides for communication between multiple master devices and multiple slave devices. FIG. 1 is a schematic diagram showing a conventional I2C device configuration 100, including two master devices 102 and 104 and two slave devices 106 and 108 coupled to each other by a serial data line/bus (SDA) 110 and a serial clock line/bus (SCL) 112. SDA 110 is configured to transmit data or address bits between master and slave devices and SCL is configured to transmit clock signals to the master and slave devices.
FIG. 2A is an exemplary timing diagram showing an exemplary communication on SDA 110 of I2C device configuration 100 in a write mode. To communicate, a master device, e.g., master device 102 or 104, transmits a start bit S followed by multiple address bits of the address identifying a slave device, e.g., slave device 106 or 108 with which the master device is communicating. The identifying address bits are followed by an RAN bit indicating whether the master device intends to write to or read from the slave device. For example, a zero (“0”) value of the R/W bit indicates a write mode while a one (“1”) value indicates a read mode. The slave devices connected to SDA 110 read the transmitted address bits. The slave device identified by the identifying address bits transmits an acknowledgement bit A, assuming the slave device exists. After receiving the acknowledgement, the master device transmits groups of data or memory address location bits (D/Add) on SDA 110 to the slave device. The slave device transmits an acknowledgement bit A or no acknowledgement bit NA on SDA 110 in response to receiving each group of bits D/Add from the master device. The transmitting of data or address bits ID/Add by the master device and transmitting of an acknowledgment bit A/NA by the slave device continue until the master device sends a stop bit P to stop the transmission or a re-start bit Sr indicating the master device wishes to retain control of the bus for another operation.
FIG. 2B is an exemplary timing diagram showing a communication on SDA 110 of I2C device configuration 100 in a read mode. Similar to the write mode, the master device, e.g., master device 102 or 104, transmits a start bit S followed by multiple address bits of the address identifying a slave device, e.g., slave device 106 or 108, with which the master device is communicating. The identifying address bits are followed by an R/W bit (R/W=1) indicating the master device intends to read from the slave device. The slave device identified by the identifying address bits transmits an acknowledgement bit A and transmits groups of data bits D to the master device. After receiving the data, the master device transmits an acknowledgement bit A or no acknowledgement bit NA. The transmitting of data from the slave device and acknowledging by the master device continues until the master device sends a stop bit P to stop the transmission or a re-start bit Sr indicating the master device wishes to retain control of the bus.
Flash memory devices can be controlled to perform several types of write operations, such as program, sector erase, block erase, and chip erase, and at least two types of read operations, such as normal read and fast read. The conventional I2C protocol cannot discern these different operations, which limits the ability to control operation of a flash memory device using the I2C protocol.